Basic Understanding of AT89C51

1. Introduction

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash erasable and programmable read only memory (EPROM). It can be erased and program to a maximum of 1000 times.

2. Block Diagram (Resources)

The chip has the following available resources:

3. Features

The chip has the following features.

1. 4K Bytes of In-System Re-programmable Flash Memory
2. Fully Static Operation: 3 MHz to 24 MHz
3. 128 x 8-bit Internal RAM
4. 32 Programmable I/O Lines
5. Two 16-bit Timer/Counters
6. Five Interrupt Sources
7. Programmable Full Duplex Serial Port
8. Low-power Idle and Power-down Modes

4. Chip Grade and Packages

The chip is available in commercial (0° C to 70° C)) and industrial (40° C to 85° C) grade with PDIP (40 pins), PQFP/TQFP (44 pins), and PLCC (44 pins) package.

5. Pin Designation

6. Pin Level Details

6.1. Power Supply Pins

VCC

1. Pin 40 provides supply voltage to the chip. The voltage source is +5v

GND

1. The pin 20 is designated for ground

6.2. External Interfacing Pins

The chip has 32 I/Os for external world interfacing. The 32 I/Os are divided into  4 ports and each port has 8 I/Os. Each port detail is the following.

Port-0

1. Port-0 is a dual-purpose port dedicated on pins 32-39
2. The pins are designated as P0.0 to P0.7 (AD0-AD7)
3. Port-0 is an 8-bit open-drain bi-directional I/O port
4. Port-0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory
5. External pull-ups are required when this port is used for general purpose output port

Port-1

1. Port-1 is a dedicated I/O port on pins 1-8
2. The pins are designated as P1.0 to P1.7
3. Port-1 is an 8-bit bi-directional I/O port with internal pull ups
4. The port-1 output buffers can sink/source four TTL inputs

Port-2

1. Port-2 is a dual-purpose port dedicated on pins 21-28
2. The pins are designated as P2.0 to P2.7 (A8-A15)
3. Port-2 is an 8-bit bi-directional I/O port with internal pull-ups
4. The port-2 output buffers can sink/source four TTL inputs
5. Port-2 emits the high-order address byte during fetches from external program memory

Port-3

1. Port-3 is a dedicated port on pins 10-17
2. The pins are designated as P3.0 to P3.7
3. Port-3 is an 8-bit bi-directional I/O port with internal pull ups
4. The Port-3 output buffers can sink/source four TTL inputs

Port-3 also serves the functions of various special features of the AT89C51 as listed below:

Port Pin	Alternate Functions
P3.0	RXD (serial input port)
P3.1	TXD (serial output port)
P3.2	INT0 (external interrupt 0)
P3.3	INT1 (external interrupt 1)
P3.4	T0 (timer 0 external input)
P3.5	T1 (timer 1 external input)
P3.6	WR (external data memory write strobe)
P3.7	RD (external data memory read strobe)

6.3. External Memory Interfacing Pins

An external memory of maximum 64KB can be attached with AT89C51.  The chip has capability to interface with memory of 8-bit data bus and maximum of 16-bit address bus. In this case port-0 and port-2 can not be used for general purpose I/Os.

PSEN

1. The output pin 29 is designated for PSEN
2. PSEN stands for “program store enable”
3. PSEN is the read strobe to external program memory
4. This pin left unconnected when internal code memory is using for program memory

ALE/PROG

1. The pin 30 is designated for ALE/PROG
2. Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory
3. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency
4. It may be used for external timing or clocking purposes

EA/VPP

1. The pin 31 is designated for EA/VPP
2. External Access Enable must be strapped to GND in order to enable the device to fetch code from external program memory
3. EA should be strapped to VCC for internal program executions

6.4. Reset Pin (RST)

1. The pin 9 is master reset input
2. Low to high pulse for 2 machine cycles resets the chip
3. For normal operation this pin is low

There are two methods of external reset circuit.

Power On Reset

1. Initially charging of capacitor makes RST pin high
2. When capacitor charges fully, it blocks DC

Manual Reset

1. Closing the switch momentarily will make RST pin High

 6.5. External Clock Pins (XTAL1 and XTAL2)

1. The AT89C51 has an on-chip oscillator but required external clock to run
2. A quartz crystal oscillator of 3 to 24 MHz value can be used
3. Two 33pF capacitors are used to stable the clock

The connections are shown in this figure.

7. Internal Peripheral Details

7.1. Timers and Counters

1. The AT89C51 has two 16-bit programmable UP timers/counters
2. They can be configured to operate either as timers or as event counters
3. The names of the two counters are T0 (pin 14) and T1 (pin 15) respectively
4. The timer mode, register is incremented in every machine cycle
5. The timer mode clock rate is 1/12 th of the oscillator frequency
6. In counter mode, the register is incremented in response to a 1 to 0 transition at its corresponding external input pin (T0 or T1)
7. It requires 2 machine cycles to detect a high to low transition
8. The maximum count rate is 1/24 th of oscillator frequency

7.2. Interrupts

1. The AT89C51 provides 5 vectored interrupts
2. There are two external interrupts (INT0, INT1)
3. The external interrupts could be negative edge triggered or low-level triggered
4. There are two timer overflow interrupts (TF0, TF1)
5. One combine serial port receiver/transmitter interrupt (RI/TI)

7.3. Serial Interface

1. The serial port of AT89C51 is full-duplex, i.e., it can transmit and receive simultaneously
2. The register SBUF is used to hold the data
3. The SBUF is physically two registers
4. One is write-only and is used to hold data to be transmitted out of the AT89C51 via TXD pin
5. The other is, read-only and holds the received data from external sources via RXD pin

8. Power Saving Modes

There are two power saving modes in AT89C51, one is call power down mode and the second is called idle mode.

8.1. Power Down Mode

1. In this mode internal oscillator is turn off and reduce power consumption enormously
2. The controller now operates using only 2v power supply, while total power consumption is less than 40uA
3. The only way to get the device back to normal mode is by reset
4. The state of all special function registers and I/O ports remains unchanged
5. By setting it back into the normal mode, the contents of the SFR register is lost, but the content of internal RAM is saved
6. Reset signal must be long enough, approximately 10mS, to enable stable operation of the internal oscillator

8.2. Idle Mode

1. The device turns off the greatest power consumer
2. The CPU unit while peripheral units such as serial port, timers and interrupt system continue operating normally consuming 6.5mA
3. The state of all registers and I/O ports remains unchanged
4. In order to exit the idle mode execute any interrupt or reset
5. Some time required for the device to stabilize and prevents undesired changes on the I/O ports.

9. Minimum Hardware Required

For download pdf version of schematics click here

10. DC Characteristics

The AT89C51 operates on (Vcc) +5v DC supply with tolerance of 20% and ambient temperature range is -40C to 85 C.

Symbol	Parameter	Condition	Min	Max	Units
VIL	Input Low voltage	Vcc = 5V ± 10%	-0.5	0.9	V
VIH	Input High voltage	Vcc = 5V ± 10%	1.9	5.5	V
VOL	Output Low voltage (Ports 1,2,3)	IOL = 1.6 mA	NA	0.45	V
VOL	Output Low voltage (Port 0)	IOL = 3.2 mA	NA	0.45	V
VOH	Output High voltage (Ports 1,2,3)	IOH = 2.23mA, VCC = 5V ± 10%	2.4	4.95	V
VOH	Output High voltage (Ports 0)	IOH = 800 μA, VCC = 5V ± 10%	NA	3.65	V
ISink	Sink Current per port pin (Ports 0,1,2,3)	VCC = 5V ± 10%	NA	-1.94	mA
ISource	Source current per port pin (Ports 1,2,3)	VCC = 5V ± 10%	NA	2.23	mA
ISource	Source current per port pin (Ports 0)	Open Drain	NA	0.08	mA
ICC	Chip Supply current	Active Mode, 12 MHz	NA	20	mA