Basic Understanding of Timer Registers in AT89C51

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1.0 Timer Pulses

The AT89C51 has two timers, both of which may be controlled, set, read, and configured individually. A timer always counts up and it is increment by 1 every machine cycle, a single machine cycle consists of 12 crystal pulses. Lets take an example to understand the timer pulses per second, if 12 MHz crystal is connected with micro-controller, thus a timer is incremented by the following formula.
timer clock

2.0 Timer Special Function Registers (SFR)

There are total six special function registers (SFRs), in witch two SFRs commonly used for both timers (Timer-0 and Timer-1). These two SFRs are used for controlling and timer mode selection. Each timer has two dedicated registers called higher byte data register and lower byte data register, basically these registers hold the timer value.
 SFR Name Description
 TMOD Timer Mode Register
 TCON Timer Control Register
 TH0Timer 0 High Byte
 TL0Timer 0 Low Byte
TH1 Timer 1 High Byte
 TL1 Timer 1 Low Byte

2.1 The TMOD SFR

The TMOD SFR is used to control the mode of operation of both timers. The high four bits (bits 4 through 7) are related to Timer 1 whereas the low four bits (bits 0 through 3) perform the exact same functions, but for timer 0. This register is byte programmable, you can not read or write individual bit.
The individual bits of TMOD have the following functions:
BitNameFunction Timer
 7 GATE1This bit is external control of timer-1. When this bit is set the timer will only run when INT1 (P3.3) is high. When this bit is clear the timer will run regardless of the state of INT1. 1
 6 C/T1This is counter-1 or timer-1 selection bit. When this bit is set the timer will count events on T1 (P3.5). When this bit is clear the timer will be incremented on every machine cycle. 1
 5 T1M1Timer-1 mode bit (see next table) 1
 4 T1M0Timer-1 mode bit (see next table) 1
 3 GATE0This bit is external control of timer-0. When this bit is set the timer will only run when INT0 (P3.2) is high. When this bit is clear the timer will run regardless of the state of INT0. 0
 2 C/T0This is counter-0 or timer-0 selection bit. When this bit is set the timer will count events on T0 (P3.4). When this bit is clear the timer will be incremented on every machine cycle. 0
 1 T0M1Timer-0 mode bit (see next table) 0
 0 T0M0Timer-0 mode bit (see next table) 0
In the above table mode of operation bits are 4,5 (timer-1) and 0,1 (timer-0). The following table shows how to use these bits for timer operation modes. Here TxM1 and TxM0 show mode bits where x is 1 for timer-1 and 0 for timer-0.
 TxM1 TxM0 Mode Mode Description
 00 0 13-bit mode
 01 1 16-bit mode
 10 2 8-bit auto re-load
 11 3 8-bit split mode

2.2 The TCON SFR

This SFR controls the timers ON/OFF and monitoring timers overflow. This register is bit programmable, you can read or write individual bit as well complete register.
 Bit Name Function Timer
 7 TF1This bit is set by the micro-controller when timer-1 overflows. 1
 6 TR1When this bit is set timer-1 is turned on. When this bit is clear timer-1 is off. 1
 5 TF0This bit is set by the micro-controller when timer-0 overflows. 0
 4 TR0When this bit is set timer-0 is turned on. When this bit is clear timer-0 is off. 0
 3 IE1Discuss in interrupt article 1
 2 IT1Discuss in interrupt article 1
 1 IE0Discuss in interrupt article 0
 0 IT0Discuss in interrupt article 0

2.3 The TH0 and TL0 SFRs

There are two 8-bit registers that hold the timer value. TH0 is called higher byte register of timer-0 and TL0 is called lower byte register of timer-0. These registers are byte programmable, you can not read or write individual bit.
timer-0 reg

2.4 The TH1 and TL1 SFRs

There are two 8-bit registers that hold the timer value. TH1 is called higher byte register of timer-1 and TL1 is called lower byte register of timer-1. These registers are byte programmable, you can not read or write individual bit.
timer-1 reg

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